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Tutorial Track

Tiva C Series Tutorials

Complete Tiva C TM4C123GXL tutorial series covering all peripherals from scratch using TivaWare SDK.

20 Chapters
20 Published
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Tiva C Series Tutorials board
1
Setting the Environment Published

Install Code Composer Studio, TivaWare SDK, and set up your first project.

2
Introduction to TivaWare Published

Overview of TivaWare peripheral driver library and ROM functions.

3
Tiva C Architecture Published

ARM Cortex-M4 core features, registers, and memory map.

4
Introduction to GPIO Published

Digital input/output, pin configuration, and basic LED/button interfacing.

5
RCC Peripheral Published

Clock configuration, PLL setup, and peripheral clock gating.

6
SysTick Peripheral Published

System tick timer for delays and periodic interrupts.

7
ADC in Tiva C Published

Analog-to-Digital Converter: single-ended, differential, sequencer modes.

8
Timers Tiva C Published

General-purpose timers: one-shot, periodic, capture, PWM modes.

9
USART in Tiva C Published

Universal Asynchronous Receiver-Transmitter for serial communication.

10
I2C Interface Published

Inter-Integrated Circuit: master/slave mode, multi-master bus.

11
Interrupt Controller (NVIC) Published

Nested Vector Interrupt Controller: priority, enabling, and handlers.

12
Memory Protection Unit (MPU) Published

MPU configuration for memory access control and protection.

13
Wire Master Module Published

1-Wire bit-bang protocol and DS18B20 temperature sensor interfacing.

14
PWM Module Published

Pulse Width Modulation for motor control and LED dimming.

15
SSI Interface Published

Synchronous Serial Interface (SPI-compatible) communication.

16
Software CRC Module Published

CRC32, CRC16, and CRC8 for firmware integrity verification.

17
DMA Controller Published

Direct Memory Access for efficient peripheral-to-memory transfers.

18
USB Controller Published

USB device and host mode controller.

19
Watchdog Timer Published

System reset on software hang using the watchdog timer.

20
Error Handling Published

Fault handlers, assert macros, and robust error management.